The present invention relates generally to a phase change memory device, and more particularly, to a technique of simultaneously writing a plurality of byte-wide data in order to reduce the total amount of writing time.
Some well known nonvolatile memory components include magnetic memory components and phase change memory (PCM) designs. The PCM components can exhibit data processing speeds similar to that of volatile Random Access Memory (RAM) components. Further PCM components enjoy the advantage of being able to conserve data even after the power is turned off.
FIGS. 1a and 1b are diagrams illustrating a conventional phase change resistor (PCR) 4.
The conventional PCR 4 comprises a phase change material (PCM) 2 inserted between a top electrode 1 and a bottom electrode 3. When a voltage and a current are imposed across the top and bottom electrodes (1,3), the temperature is raised in the PCM 2, which results in altering the electric conductive properties, and thereby the resistance changes as a function of the state of the PCM 2.
The PCM 2 can include any number of different materials, such as AgLnSbTe. The PCM 2 often times includes a chalcogenide having at least one of the chalcogen elements (S, Se, Te) as a main ingredient, and containing other ingredients such as germanium and antimony. One PCM 2 of interest is the germanium antimonic tellurium consisting of Ge—Sb—Te (Ge2Sb2Te5).
FIGS. 2a and 2b are diagrams illustrating a principle of the conventional PCR 4.
As shown in FIG. 2a, the PCM 2 can maintain its crystalline morphology when a relatively low current of less than a threshold value flows through the PCM 4. As a result, of the highly ordered crystalline morphology of the PCM 2, the crystalline PCM 2 exhibits a relatively low resistance.
As shown in FIG. 2b, the crystalline morphology of the PCM 2 can be induced to melt when a current of more than a threshold value is imposed across the PCR 4. As a result of raising the temperature above the crystalline melting temperature coupled with cooling the melted PCM 2 relatively rapidly, the crystalline morphology of the PCM 2 can be transformed into an alternate solid amorphous morphology. It is thought that because of the increased number or increased density of crystal imperfections in these amorphous states, the amorphous PCM 2 exhibits a higher electrical resistance as compared to the crystalline PCM 2.
Accordingly, one can exploit this difference in physical properties by designing a PCR 4 to be configured to store nonvolatile data corresponding to the two resistance states. One could arbitrarily assign a data “1” state to refer to when the PCR 4 exhibits a relatively low resistance state. Likewise, one could arbitrarily assign a data “0” state to refer to when the PCR 4 exhibits a relatively high resistance state. Accordingly, binary logic states can be stored in these types of PCM devices without the need for powering these devices.
When heat is generated from an electrical current flowing is across the top electrode 1 and the bottom electrode 3 of the PCR 4, the solid state morphology of the PCM 2 can be transformed from crystalline to an amorphous state if the heat raises the temperature above the melting point and if the subsequent cooling step is performed rapidly.
In contrast, when heat is generated from an low amount of electrical current flowing across the top electrode 1 and the bottom electrode 3 of the PCR 4, the solid state morphology of the PCM 2 in the crystalline state can be maintained. As long as the current is relatively low so that the resultant temperature never rises above the melting point then the PCM can be maintained in a crystalline state. As mentioned above, when the PCR 4 is in a crystalline state it exhibits a relatively lower resistance which can be arbitrarily defined to be a set state. On the other hand, when a high electrical current flows across the top electrode 1 and the bottom electrode 3 of the PCR 4, the PCM can be transformed into an amorphous state from the heating and from the rapid cooling. As a consequence when the PCR 4 is in the amorphous state it exhibits a relatively higher resistance which can be arbitrarily defined as a reset state. A physical property difference between these two morphological phases is the change in the electric resistance.
A low voltage is applied to the PCR 4 for a long time in order to allow the PCM 2 to transform into the crystalline state and thus write the set state in a write mode. On the other hand, a high voltage is applied to the PCR 4 for a short time in order to allow the melted PCM 2 to anneal into the amorphous state and thus write the reset state in the write mode.
In the operation of conventional phase change memory devices, when a write cycle is initiated, new data is always written regardless of what data, i.e., regardless of what solid state the PCM 2 is at, resides in the selected phase change resistor PCR 4.
FIGS. 3 and 4 are diagrams illustrating a write cycle of a conventional phase change memory device.
During a write cycle (1), one byte-width data is written in a phase change resistor PCR 4 after a first write command is received. During an nth write cycle, one byte width data is written in the phase change resistor PCR 4 after an nth write command is received.
Heat is generated when a current flows between the top electrode 1 and the bottom electrode 3 of the PCR 4 for a given time. As a result, a state of the PCM 2 can be changed to be either crystalline or amorphous depending on temperature and the annealing step applied at the top electrode 1 and the bottom electrode 3.
When a low current flows for a given time, the PCM 2 solid state morphology can be transformed into a crystalline morphology as a result of a low temperature heating state and consequently a slow annealing so that the PCR 4 results in producing a low resistor at a set state. On the other hand, when a high current flows for a given time, the solid state morphology of the PCM 2 can be transformed into an amorphous solid state morphology as a result of the induced high temperature heating state coupled with an abrupt annealing so that the PCR 4 results in producing a high resistor which could then be arbitrarily assigned to be a reset state. Accordingly, this difference between these two different solid state morphologies, i.e., crystalline and amorphous morphological solid state phases, represents a controllable electric resistance change.
A low voltage is applied to the PCR 4 for a relatively long time period in order to gently drive the phase transition between the solid and liquid state and to provide a relatively gentle annealing condition that results in forming a crystalline solid state morphology in the PCM 2 which thereby writes the set state in a write mode. On the other hand, a high voltage is applied to the PCR 4 for a relatively short time period in order to drive the phase transistion between the solid and liquid states and to provide an abrupt annealing condition that results in forming an amorphous solid state morphology in the PCM 2 which thereby writes the reset state in the write mode.
In the conventional phase change memory device, when a write cycle starts, new data is always written unconditionally in the selected phase change resistor PCR 4. As a result, conventional phase change memory devices require a considerable amount of time and energy to set/reset the data in the cells.
During a single write cycle, writing data one byte wide is always written in the phase change resistor PCR depending on a write command. As a result, a considerable amount of time is needed to write data having one byte-width in the phase change resistor PCR is required using conventional phase change memory devices.